Recently, a multi-layer wiring technique for laminating circuit elements of a semiconductor device is becoming important with the trend of higher processing speed and fineness of a semiconductor device. With the progress of the multi-layer wiring technique, there has been posed a problem of irregularities formed on the surface of a sample. For example, in the case where a circuit pattern is formed on the sample surface by an optical exposure device (hereinafter referred to as a stepper), it is necessary to accurately adjust the focal point of the stepper onto the sample surface. However, when the irregularities are present on the sample surface, adjustment of the focal point on the sample surface is difficult, resulting in an occurrence of serious problem of inferior resolution.
For overcoming such an inconvenience as described above, the technique for planarizing the surface of a semiconductor device has been demanded.
In Japanese Patent Laid-open No. Hei 10-146750, there is disclosed a technique for planarizing the fine irregularities formed on the surface of a semiconductor device. According to the technique disclosed in the publication, a wafer substrate to be processed held on a rotating holder is pressed on the surface of a polishing pad held on a rotating table, and a polishing liquid containing loose abrasive grain is supplied between the polishing pad and the wafer to be processed, whereby the surface of the semiconductor wafer substrate can be polished to planarize the fine irregularities.
Since the polishing pad used for the purpose of polishing as described above becomes crushed in surface as it is used, dressing is carried out therefor with suitable frequency. Dressing termed herein is that a polishing pad is shaved by a diamond grindstone (hereinafter referred to as a dressing tool) or the like for dressing to provide a suitable surface roughness, as disclosed in Japanese Patent Laid-open No. Hei 10-180618.